1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of transistors having strained channel regions by using an embedded strained layer in the drain and source regions to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel, due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions raises a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques, it has been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the problems encountered with the process adaptations associated with device scaling. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Therefore, in one approach, the hole mobility of PMOS transistors is enhanced by forming a strained silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create strain in the adjacent silicon channel region. To this end, the drain and source extension regions of the PMOS transistors are formed on the basis of ion implantation. Thereafter, respective sidewall spacers are formed at the gate electrode as required for the definition of the deep drain and source junctions and the metal silicide in a later manufacturing stage. Prior to the formation of the deep drain and source junctions, these regions are selectively recessed based on the sidewall spacers, while the NMOS transistors are masked. Subsequently, a highly doped silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth techniques. Typically, the strained silicon/germanium is provided with a certain degree of “overfill” during the epitaxial growth in order to reduce the consumption of the desired strained silicon/germanium material during a silicidation process for forming a metal silicide in the drain and source regions for obtaining a reduced contact resistance. After the selective growth process and the formation of respective drain and source regions in the N-channel transistors on the basis of conventional implantation techniques, an anneal process is performed to activate dopants and re-crystallize implantation-induced damage. Moreover, during the anneal process, the dopants within the strained silicon/germanium layer are also diffusing, thereby forming respective PN junctions outside the strained silicon/germanium layer and within the adjacent silicon material.
FIG. 1 schematically illustrates a corresponding P-channel transistor 100 formed on a bulk substrate 101 during a respective anneal process 108. In this manufacturing stage, the transistor 100 may comprise a gate electrode 104 including a sidewall spacer structure 106 and formed on a gate insulation layer 105 that separates the gate electrode 104 from a body region 102 in which a conductive channel may build up when applying an appropriate control voltage to the gate electrode 104. Adjacent to the body region 102, extension regions 103 may be located that comprise a moderately high concentration of a P-type dopant. Next to the extension regions 103 are formed highly P-doped strained silicon/germanium regions 107.
The transistor 100 may be formed on the basis of well-established techniques as previously described. During the anneal process 108, the dopants in the extension regions 103 and in the strained regions 107 may diffuse, as indicated by the arrows, to finally obtain respective PN junctions 109 that are completely located within the silicon-based region 102. Thereafter, a metal silicide (not shown) may be formed in the excess portions 107A of the strained silicon/germanium regions 107 and in the gate electrode 104 on the basis of well-established silicidation techniques.
This process technique may provide significant advantages for bulk devices where the respective cavities for receiving the strained silicon/germanium material may be etched deep into the silicon substrate and the PN junctions may be positioned within the silicon material, thereby providing low leakage junctions. However, it turns out that, for silicon-on-insulator (SOI) devices, this strategy may be less efficient, due to the limited thickness of the silicon layer and increased floating body effects when transistor architectures without additional body contacts are considered.
In view of the above-described situation, there exists a need for an improved technique for increasing the performance of SOI transistors by the use of strained semiconductor materials, while substantially avoiding or at least reducing one or more of the above-identified problems.